1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus and driving method thereof, in which scan electrodes are scanned according to one of a plurality of scan types and a last sustain pulse of sustain pulses applied to scan electrodes or sustain electrodes is controlled.
2. Background of the Related Art
In general, a plasma display panel comprises a front panel and a rear panel. Barrier ribs formed between the front panel and the rear panel form one cell. Each cell is filled with a primary discharge gas, such as neon (Ne), helium (He) or a mixed gas of Ne+He, and an inert gas containing a small amount of xenon (Xe). A plurality of these cells form one pixel. For example, a red (R) cell, a green (G) cell and a blue (B) cell form one pixel. If the inert gas is discharged with a high frequency voltage, it generates vacuum ultraviolet rays. Phosphors formed between the barrier ribs are excited to display images. The plasma display panel can be made thin and light, and has thus been in the spotlight as the next-generation display devices.
FIG. 1 is a view showing the construction of a general plasma display panel.
As shown in FIG. 1, the plasma display panel comprises a front substrate 100 and a rear substrate 110. In the front substrate 100, a plurality of sustain electrode pairs in which scan electrodes 102 and sustain electrodes 103 are formed in pairs is arranged on a front glass 101 serving as a display surface on which images are displayed. In the rear substrate 110, a plurality of address electrodes 113 crossing the plurality of sustain electrode pairs is arranged on a rear glass 111 serving as a rear surface. At this time, the front substrate 100 and the rear substrate 110 are parallel to each other with a predetermined distance therebetween.
The front substrate 100 comprises the pairs of scan electrodes 102 and sustain electrodes 103, which mutually discharge one another and maintain the emission of a cell within one discharge cell. In other words, each of the scan electrode 102 and the sustain electrode 103 has a transparent electrode (a) formed of a transparent ITO material and a bus electrode (b) formed of a metal material. The scan electrodes 102 and the sustain electrodes 103 are covered with one or more dielectric layers 104 for limiting a discharge current and providing insulation among the electrode pairs. A protection layer 105 having Magnesium Oxide (MgO) deposited thereon is formed on the dielectric layers 104 so as to facilitate discharge conditions.
In the rear substrate 110, barrier ribs 112 of stripe form (or well form), for forming a plurality of discharge spaces, i.e., discharge cells are arranged parallel to one another. Furthermore, a plurality of address electrodes 113, which generate vacuum ultraviolet rays by performing an address discharge, are disposed parallel to the barrier ribs 112. R, G and B phosphor layers 114 that radiate a visible ray for displaying images during an address discharge are coated on a top surface of the rear substrate 110. A dielectric layer 115 for protecting the address electrodes 113 is formed between the address electrodes 113 and the phosphor layers 114.
In the plasma display panel constructed above, the electrodes are constructed in matrix form. This will be described with reference to FIG. 2.
FIG. 2 is a view schematically showing the arrangement of electrodes of a three-electrode AC surface-discharge type plasma display panel (hereinafter referred to as “PDP”).
Referring to FIG. 2, the three-electrode AC surface-discharge type PDP in the related art comprises scan electrodes Y1 to Yn and sustain electrodes Z formed on an upper plate, and address electrodes X1 to Xm formed on a lower plate such that they cross the scan electrodes Y1 to Yn and the sustain electrodes Z.
Discharge cells 200 for displaying any one of red, green and blue are disposed at the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z, and the address electrodes X1 to Xm in matrix form.
A dielectric layer (not shown) and an MgO protection layer (not shown) are laminated on the upper plate in which the scan electrodes Y1 to Yn and the sustain electrodes Z are formed.
Barrier ribs for preventing optical and electrical interference among neighboring discharge cells 200 are formed on the lower plate in which the address electrodes X1 to Xm are formed. Phosphors, which are excited by ultraviolet rays to emit a visible ray, are formed on surfaces of the lower plate and the barrier ribs.
An inert mixed gas such as He+Xe, Ne+Xe or He+Xe+Ne is injected into discharge spaces between the upper plate and the lower plate of the PDP.
A method of implementing gray levels of an image in the plasma display apparatus constructed above will be described with reference to FIG. 3.
FIG. 3 is a view illustrating a method of implementing gray levels of an image of a plasma display apparatus in the related art.
As shown in FIG. 3, in order to represent image gray levels of the plasma display panel in the related art, one frame is divided into several sub-fields having a different number of emissions. Each of the sub-fields is divided into a reset period (RPD) for initializing the entire cells, an address period (APD) for selecting a cell to be discharged, and a sustain period (SPD) for implementing gray levels depending on the number of discharges. For example, if it is sought to display images with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 seconds is divided into eight sub-fields (SF1 to SF8) as shown in FIG. 2. Each of the eight sub-fields (SF1 to SF8) is again divided into a reset period, an address period and a sustain period.
The reset period and the address period of each sub-field are the same every sub-field. An address discharge for selecting a cell to be discharged is generated because of a voltage difference between the address electrodes and the scan electrodes (i.e., transparent electrodes). The sustain period is increased in the ratio of 2n (where n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field. Since the sustain period is varied every sub-field as described above, gray levels of an image are represented by controlling the sustain period of each sub-field, i.e., a sustain discharge number.
FIG. 4 is a view illustrating equivalent capacitance (C) of a plasma display panel.
Referring to FIG. 4, the equivalent capacitance (C) of the plasma display panel comprises equivalent capacitance (Cm1) between the data electrodes, such as a data electrode X1 and a data electrode X2, equivalent capacitance (Cm2) between the data electrode and the scan electrodes, such as the data electrode X1 and a scan electrode Y1, and equivalent capacitance (Cm2) between the data electrode and the sustain electrode such as the data electrode X1 and a sustain electrode Z1.
Meanwhile, the state of a voltage applied to the scan electrode Y or the data electrode X is changed according to the operation of a switching element included in a drive IC, such as a scan drive IC, for driving the scan electrode Y by supplying a scan pulse to the scan electrode Y in an address period, and a drive IC, such as a data driver IC, for driving the data electrode X by supplying a data pulse to the data electrode X in an address period. Therefore, the displacement current (Id) that is generated the aforementioned equivalent capacitance (Cm1) and the equivalent capacitance (Cm2) flows through the data driver IC through the data electrode.
As described above, if the equivalent capacitance of the plasma display panel increases, the amount of the displacement current (Id) flowing through the data driver IC is increased. If the switching number of the data driver IC is increased, the amount of the displacement current (Id) is increased. The switching number of the data driver IC is varied depending on input image data.
More particularly, in the case of a specific pattern in which a logic value of image data is repeated between 0 and 1, the amount of the displacement current flowing through the data driver IC is excessively increased. Therefore, there is a problem in electrical damage such as a burnt data driver IC.
FIG. 5 is a waveform showing an example of a driving waveform of a general plasma display panel. FIGS. 11a to 6e are views showing, step by step, the distribution of wall charges within a discharge cell, which is varied according to the driving waveform as shown in FIG. 5.
The driving waveform of FIG. 5 will be described in connection with FIGS. 11a to 6e. 
Referring to FIG. 5, each of sub-fields (SFn−1, SFn) includes a reset period (RP) for initializing the discharge cells 1 of the entire screen, an address period (AP) for selecting discharge cells, a sustain period (SP) for sustaining the discharge of selected discharge cells 1, and an erase period (EP) for erasing wall charges within the discharge cells 1.
In the erase period (EP) of the (n−1)th sub-field (SFn−1), an erase ramp waveform (ERR) is applied to the sustain electrodes Z. during the erase period (EP), 0V is applied to the scan electrodes Y and the address electrodes X. The erase ramp waveform (ERR) is a positive ramp waveform whose voltage gradually rises from 0V to a positive sustain voltage (Vs). An erase discharge is generated between the scan electrodes Y and the sustain electrodes Z within on-cells in which the sustain discharge is generated by the erase ramp waveform (ERR). Wall charges within the on-cells are erased by the erase discharge. As a result, each of the discharge cells 1 has the wall charge distribution as shown in FIG. 6a soon after the erase period (EP).
In a set-up period (SU) of the reset period (RP) where the nth sub-field (SFn) begins, a positive ramp waveform (PR) is applied to all the scan electrodes Y, and 0V is applied to the sustain electrodes Z and the address electrodes X. A voltage on the scan electrodes Y gradually rises from the positive sustain voltage (Vs) to a reset voltage (Vr), which is higher than the positive sustain voltage (Vs), by means of the positive ramp waveform (PR) of the set-up period (UP). A dark discharge in which light is rarely generated is generated between the scan electrodes Y and the address electrodes X within the discharge cells of the entire screen as well as between the scan electrodes Y and the sustain electrodes Z by means of the positive ramp waveform (PR). As a result of this dark discharge, positive wall charges remain on the address electrodes X and the sustain electrodes Z immediately after the set-up period (SU), and negative wall charges remain on the scan electrodes Y, as shown in FIG. 6b. While the dark discharge is generated in the set-up period (SU), a gap voltage (Vg) between the scan electrodes Y and the sustain electrodes Z and a gap voltage between the scan electrodes Y and the address electrodes X are initialized to a voltage close upon a firing voltage (Vf) which can generate a discharge.
After the set-up period (SU), in a set-down period (SD) of the reset period (RP), a negative ramp waveform (NR) is applied to the scan electrodes Y. At the same time, the positive sustain voltage (Vs) is applied to the sustain electrodes Z and 0V is applied to the address electrodes X. A voltage on the scan electrodes Y gradually falls from the positive sustain voltage (Vs) to a negative erase voltage (Ve) by means of the negative ramp waveform (NR). A dark discharge is generated between the scan electrodes Y and the sustain electrodes Z as well as between the scan electrodes Y and the address electrodes X within the discharge cells of the entire screen by means of the negative ramp waveform (NR). As a result of the dark discharge of the set-down period (SD), the wall charge distribution within each of the discharge cells 1 is changed to an optimal address condition, as shown in FIG. 6c. At this time, excessive wall charges unnecessary for an address discharge are erased from the scan electrodes Y and the address electrodes X within each of the discharge cells 1 except for a predetermined amount of the wall charges. The wall charges on the sustain electrodes Z have its polarity inverted from a positive polarity to a negative polarity as negative wall charges moved from the scan electrodes Y are accumulated on the sustain electrodes Z. While the dark discharge is generated in the set-down period (SD) of the reset period (RP), a gap voltage between the scan electrodes Y and the sustain electrodes Z and a gap voltage between the scan electrodes Y and the address electrodes X becomes close to the firing voltage (Vf).
In the address period (AP), while negative scan pulses (−SCNP) are sequentially applied to the scan electrodes Y, a positive data pulse (DP) is applied to the address electrodes X in synchronization with the scan pulse (−SCNP). A voltage of the scan pulse (−SCNP) is a scan voltage (Vsc), which falls from 0V or a negative scan bias voltage (Vyb) close to 0V to a negative scan voltage (−Vy). A voltage of the data pulse (DP) is a positive data voltage (Va). During the address period (AP), a positive Z bias voltage (Vzb) lower than the positive sustain voltage (Vs) is applied to the sustain electrodes Z. In a state where the gap voltage is adjusted to a voltage close to the firing voltage (Vf) immediately after the reset period (RP), an address discharge is generated between the scan electrodes Y and the address electrodes X while the gap voltage between the electrodes Y, X exceeds the firing voltage (Vf) within on-cells to which the scan voltage (Vsc) and the data voltage (Va) are applied. The first address discharge between the scan electrode Y and the address electrode X generates priming charged particles within the discharge cells, and thus induces a second discharge between the scan electrodes Y and the sustain electrodes Z, as shown in FIG. 6d. The wall charge distribution within on-cells in which the address discharge is generated is shown in FIG. 6e. 
Meanwhile, the wall charge distribution within off-cells in which the address discharge is not generated substantially keeps the state of FIG. 6c. 
In the sustain period (SP), sustain pulses (SUSP) of a positive sustain voltage (Vs) are alternately applied to the scan electrodes Y and the sustain electrodes Z. A sustain discharge is generated between the scan electrodes Y and the sustain electrodes Z within on-cells selected by the address discharge every sustain pulse (SUSP) owing to the wall charge distribution of FIG. 6e. To the contrary, a discharge is not generated within off-cells during the sustain period. This is because the gap voltage between the scan electrodes Y and the sustain electrodes Z cannot exceed the firing voltage (Vf) when the first positive sustain voltage (Vs) is applied to the scan electrodes Y since the wall charge distribution of the off-cells is kept to the state of FIG. 6c. 
In the conventional plasma display apparatus, however, several discharges are generated in order to control the initialization and wall charges of the discharge cells 1 through the erase period (EP) of the (n−1)th sub-field (SFn−1) and the reset period (RP) of the nth sub-field (SFn). Therefore, problems arise because a dark room contrast value is lowered and the contrast ratio is lowered accordingly.
Furthermore, in the conventional plasma display apparatus, in the case where negative wall charges are excessively accumulated on the scan electrodes Y since wall charges are not smoothly erased in the erase period (EP) of the (n−1)th sub-field (SFn−1), a dark discharge is not generated in the set-up period (SU) of the nth sub-field (SFn). If the dark discharge is not normally generated in the set-up period (SU) as described above, discharge cells are not initialized. In this case, to generate s discharge in the set-up period, the reset voltage (Vr) should become high. If the dark discharge is not generated in the set-up period (SU), a condition within the discharge cells immediately after the reset period does not become an optimal address condition. This results in an abnormal discharge or erroneous discharge. In addition, if positive wall charges are excessively accumulated on the scan electrodes Y soon after the erase period (EP) of the (n−1)th sub-field (SFn−1), a strong discharge is generated when the positive sustain voltage (Vs), i.e., a start voltage of the positive ramp waveform (PR), is applied to the scan electrodes Y in the set-up period (SU) of the nth sub-field (SFn). Therefore, initialization is not uniform over the entire cells. These problems will be described in detail below with reference to FIG. 7.
FIG. 7 is a view illustrating variation in an externally applied voltage and a gap voltage within a discharge cell between scan electrodes and sustain electrodes in a set-up period when the plasma display panel is driven according to the driving waveform as shown in FIG. 5.
FIG. 7 shows an externally applied voltage (Vyz) between the scan electrodes Y and the sustain electrodes Z in the set-up period (SU) and a gap voltage (Vg) within a discharge cell. The externally applied voltage (Vyz), which is indicated by a solid line in FIG. 7, is an external voltage applied to the scan electrodes Y and the sustain electrodes Z. Since 0V of is applied to the sustain electrodes Z, the externally applied voltage (Vyz) is substantially the same as a voltage of the positive ramp waveform (PR). In FIG. 7, dotted lines {circle around (1)}{circle around (2)} and {circle around (3)} indicate gap voltages (Vg) formed in a discharge gas by means of the wall charges within the discharge cell. The gap voltages (Vg) are varied as indicated by dotted lines {circle around (1)}{circle around (2)} and {circle around (3)} because the amount of wall charges within the discharge cells is varied depending on whether a discharge has been generated in a previous sub-field or not. The relation between the externally applied voltage (Vyz) between the scan electrodes Y and the sustain electrodes Z and the gap voltage (Vg) formed in the discharge gas within the discharge cell can be expressed in the following Equation 1.Vyz=Vg+Vw  [Equation 1]
In FIG. 7, the gap voltage (Vg) of {circle around (1)} refers to a case where wall charges within a discharge cell are sufficiently erased and the wall charges are sufficiently small. The gap voltage (Vg) increases in proportion to the externally applied voltage (Vyz), but generates a dark discharge if it reaches the firing voltage (Vf). The gap voltage within the discharge cells are initialized to the firing voltage (Vf) by the dark discharge.
In FIG. 7, the gap voltage (Vg) of {circle around (2)} defers to a case where a strong discharge is generated during the erase period (EP) of the (n−1)th sub-field (SFn−1) and thus inverts the polarity of wall charges in the wall charge distribution within the discharge cells. At this time, the polarity of wall charges accumulated on the scan electrodes Y soon after the erase period (EP) is inverted to a positive polarity because of the strong discharge. This case happens when the uniformity of discharge cells is low or a tilt of the erase ramp waveform (ERR) is varied depending on variation in temperature when the size of a PDP is large. In this case, as the initial gap voltage (Vg) excessively rises as indicated by {circle around (2)} FIG. 7, the gap voltage (Vg) exceeds the firing voltage (Vf) while the positive sustain voltage (Vs) is applied to the scan electrodes Y in the set-up period (SU). Therefore, a strong discharge is generated. Since the discharge cells are not initialized to the wall charge distribution of an optimal address condition, i.e., the wall charge distribution of FIG. 6c by means of the strong discharge in the set-up period (SU) and the set-down period (SD), an address discharge may be generated in off-cells that should be turned off. In other words, if a strong erase discharge is generated in the erase period prior to the reset period, an erroneous discharge can be generated.
In FIG. 7, the gap voltage (Vg) of {circle around (3)} refers to a case where a wall charge distribution within discharge cells, which are formed as a result of a sustain discharge generated immediately before an erase discharge, keeps intact because the erase discharge is not generated or very weakly generated during the erase period (EP) of the (n−1)th sub-field (SFn−1). This will be described in more detail. As shown in FIG. 7, the last sustain discharge is generated when the sustain pulse (SUSP) is applied to the scan electrodes Y. As a result of the last sustain discharge, negative wall charges remain on the scan electrodes Y and positive wall charges remain on the sustain electrodes Z. However, although these wall charges must be erased in order for initialization to be normally performed in a next sub-field, the polarity of the wall charges keeps intact if the erase discharge is not generated or the erase discharge is very weakly generated. The reason why the erase discharge is not generated or is very weakly generated is that the uniformity of discharge cells in a PDP is very low or a tilt of the erase ramp waveform (ERR) is changed depending on a variation in temperature. In this case, since the initial gap voltage (Vg) is very low, i.e., a negative polarity as shown in {circle around (3)} of FIG. 7, the gap voltage (Vg) within the discharge cells does not reach the firing voltage (Vf) even if the positive ramp waveform (PR) rises up to the reset voltage (Vr) in the set-up period. Therefore, a dark discharge is not generated in the set-up period (SU) and the set-down period (SD). Consequently, if an erase discharge is not generated or is very weakly generated in the erase period prior to the reset period, an erroneous discharge or an abnormal discharge is generated because initialization is not normally performed.
In the case of {circle around (2)} in FIG. 7, the relation between the gap voltage (Vg) and the firing voltage (Vf) can be expressed in the following Equation 2. In the case of {circle around (3)} in FIG. 7, the relation between the gap voltage (Vg) and the firing voltage (Vf) can be expressed in the following Equation 3.Vgini+Vs>Vf  [Equation 2]Vgini+Vr<Vf  [Equation 3]
where Vgini is an initial gap voltage immediately before the set-up period (SU) as can be seen from FIG. 7.
In consideration of the above problem, a gap voltage condition (or a wall voltage condition) for enabling initialization to be normally performed in the erase period (EP) and the reset period (RP) can be expressed in the following Equation 4, which fulfills both Equations 2 and 3.Vf−Vr<Vgini<Vf−Vs  [Equation 4]
As a result, if the initial gap voltage (Vgini) does not fulfill the condition of Equation 4 prior to the set-up period (SU), the conventional plasma display apparatus can generate an erroneous discharge, miss-discharge or abnormal discharge, and has a narrow operational margin. In other words, to secure operational reliability and operational margin in the conventional plasma display apparatus, an erase operation in the erase period (EP) should be normally performed. However, the erase operation can be performed abnormally depending on the uniformity of discharge cells and a use temperature of a PDP, as described above.
Furthermore, in the conventional plasma display apparatus, an erroneous discharge, miss-discharge or an abnormal discharge can be generated due to excessive spatial charges occurring under a high-temperature environment and an unstable wall charge distribution due to the amount of active motion of the spatial charges. Therefore, a problem arises because operational margin is narrowed. This will be described in detail in connection with FIGS. 8a to 8c. 
FIGS. 8a to 8c are views illustrating spatial charges and the behavior of the spatial charges when the plasma display panel is driven according to the driving waveform as shown in FIG. 5 under high temperature environment.
The amount of spatial charges generated upon discharge and the amount of motion thereof under high temperature environment, are greater than those at room temperature or a low temperature. Therefore, in a sustain discharge of a (n−1)th sub-field (SFn−1), lots of spatial charges are generated. Lots of spatial charges 300 within the discharge space remain active even immediately after the set-up period (SU) of the nth sub-field (SFn), as shown in FIG. 8a. 
If the data voltage (Va) is applied to the address electrodes X and the scan voltage (−Vy) is applied to the scan electrodes Y during the address period in a state where the spatial charges 300 having active motion exist in the discharge space, as shown in FIG. 8a, negative spatial charges 300 are recombined with negative wall charges that have been accumulated on the scan electrodes Y as a result of the set-up discharge of the set-up period (SU), and negative spatial charges 300 are also recombined with positive wall charges that have been accumulated on the address electrodes Y as a result of the set-up discharge of the set-up period (SU), as shown in FIG. 8b. 
As a result, as shown in FIG. 8c, the negative wall charges on the scan electrodes Y, which have been formed by the set-up discharge, and the positive wall charges on the address electrodes X, which have been formed by the set-up discharge, are erased. Although the data voltage (Va) and the scan voltage (−Vy) are applied to the address electrodes X and the scan electrodes Y, the gap voltage (Vg) does not reach the firing voltage (Vf). Therefore, an address discharge is not generated. Therefore, if the driving waveform as shown in FIG. 5 is applied to a PDP used under high temperature environment, a problem arises because miss-writing of on-cells is frequently generated.
FIG. 8d is a view illustrating an erroneous discharge depending on the temperature in the plasma display apparatus that is operated according to the driving waveform depending on the driving method in the related art.
Referring to FIG. 8d, in the plasma display apparatus that is operated according to the driving waveform depending on the driving method in the related art, in the case where the temperature around the panel is relatively high, the ratio in which spatial charges 401 and wall charges 400 within a discharge cell are recombined is increased. Therefore, an erroneous discharge is generated because an absolute amount of wall charges that take part in a discharge is reduced. The aforementioned spatial charges 401 are charges existing in the spaces within the discharge cell and do not take part in a discharge unlike the wall charges 400.
For example, the ratio in which the spatial charges 401 and the wall charges 400 within a discharge cell are recombined in the address period is increased and the amount of the wall charges 400 taking part in the address discharge is decreased. This makes unstable the address discharge. In this case, a time where the spatial charges 401 and the wall charges 400 can be recombined is sufficiently secured as the order of addressing is later. This further makes unstable the address discharge. Therefore, a high temperature erroneous discharge, such as that discharge cells, which have been turned on in the address period, are turned off in the sustain period, is generated.
Furthermore, in the case where the temperature around the panel is relatively high, if a sustain discharge is generated in the sustain period, the speed of the spatial charges 401 becomes fast during a discharge. This increases the ratio in which the spatial charges 401 and the wall charges 400 are recombined. Therefore, the amount of the wall charges 400 that participate in the sustain discharge is reduced due to the recombination of the spatial charges 401 and the wall charges 400 after any one sustain discharge, which prevents a next sustain discharge form occur. Therefore, a problem arises because a high temperature erroneous discharge is generated.